Ever since the presence of integrated circuit (IC), the minimum channel width of the transistor in a chip has decreased with the improvement of the semiconductor process, the number of the transistors integrated in a chip has increased with stronger function and wider applications. As shown in FIG. 1, a conventional lateral cellular CMOS array 100 has a configuration of symmetric structure, in which polygon regions 102 and 108 are sources, polygon regions 104 and 106 are drains, each of them includes four contacts 112, and the sources 102 and 108 further include pick up contact 114 of the substrate. In this exemplary layout, the regions 102, 104, 106 and 108 are N+ type, poly silicon mesh 110 is used for the gates between the sources and the drains, the length and the width of the gate 110 between adjacent source/drain are L and W, respectively, and the drains 104 and 106 are lightly doped to form N type double drain (NDD) for this cellular CMOS array 100 available to be used as a high-voltage device.
Due to the rapid development of the semiconductor industry, high density and low cost are the goals each semiconductor fab chases, and it is therefore desired a denser cellular CMOS array for a wafer of the same size to be diced into more chips to lower the cost.